> ## Documentation Index
> Fetch the complete documentation index at: https://docs.koppar.ai/llms.txt
> Use this file to discover all available pages before exploring further.

# Design rules

> What Koppar decides for a PCB and what you can state: board size, 1 to 8 copper layers, hand-made boards, net classes, differential pairs, rail widths and fab presets.

Before placement, one planning call turns the circuit into a board plan. Some of it is decided from the circuit. Some of it is read from what you said.

## What you can state

Facts stated in the prompt are carried as stated facts, not as suggestions. They are never overridden by the planner.

| You say | Effect |
| - | - |
| "four mounting holes" | That many holes, in the corners of the board as sized. They move with the outline if it grows. |
| "50 by 30 mm", "25 mm wide" | The outline. A width or a height may be stated alone. |
| "two layers", "four layers" | The copper layer count: 1, 2, 4, 6 or 8. |
| "single-sided", "copper on one side" | One copper face and no vias: the solder side when any part is through-hole, the component side on an all-SMD board. A net the one face cannot carry is reported open, for a wire strap. |
| "made by hand", "home-etched", "toner transfer" | Hand-etch design rules: 0.6 mm tracks, 0.5 mm gaps, 1.6/0.8 mm strap vias, 1 mm from the edge. The Gerbers come with a 1:1 artwork PDF of the copper face. |
| "1 mm tracks", "0.4 mm clearance" | That track width or gap as the board's default rule. |

Everything else, say it and the planner takes it as intent: which connector sits on which edge, which parts group together, which sit near which, what stays off the board.

## What the planner decides

* **Outline.** Derived from the parts and the stated size.
* **Layers.** 2 by default. 4 when the circuit needs it, or when a 2-layer board cannot close.
* **Net classes.** Every net is a plain signal track unless a class says otherwise. Classes come from the circuit, from what you state, or from the net name.
* **Edge parts, groups, keepouts.** Connectors on edges, decoupling by its IC, antennas kept clear of copper.

## Net classes

| Class | How it is set | What the router does |
| - | - | - |
| Power rail | Declared with a current, or inferred from the net name | Width from IPC-2221 for that current, 4 A is about 2 mm. Inferred rails are widen-only. Capped at 5 mm. |
| Differential pair | Declared, or inferred from `_P`/`_N` names for USB, CAN, MIPI, HDMI, LVDS, PCIe and Ethernet | Routed as a pair with the declared gap. Coupling, skew and the width applied are reported. |
| Length-matched group | Declared with a tolerance | Lengths matched within the tolerance; residuals reported. |
| Ground | Always | Poured on every board. |

Widths are a target and connectivity is the contract: where the geometry will not take the class width, the net is routed narrower rather than left open, and the width applied is reported.

The classes are written into the KiCad project, so KiCad's DRC checks the same rules Koppar did.

## Fab presets

The project file carries the floors the copper is legal at: the router's minimum track width, the minimum drill, and a 0.3 mm copper-to-edge clearance. The JLCPCB preset applies that fab's published minimums as custom DRC rules, including the per-feature limits for plated rings and hole-to-track spacing that KiCad's standard DRC does not cover. The preset note states that 0.15 mm drills and tracks under 0.127 mm cost extra at that fab.

## Your own plan

Over MCP, the CLI or REST, the plan is yours. `get_board_context` returns the parts, their sizes, the stated facts and the plan schema; `start_board` takes a JSON object with `board`, `stated`, `edge`, `chain`, `groups`, `near`, `side`, `fixed`, `keepouts` and `netClasses`. The plan is clamped to what the board can take and returned as applied.


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