> ## Documentation Index > Fetch the complete documentation index at: https://docs.koppar.ai/llms.txt > Use this file to discover all available pages before exploring further. # Verification > Every check a Koppar design passes: ERC and KiCad ERC on the schematic, sourcing and footprint checks, KiCad DRC with fab minimums, and the release gate. Koppar is built so that a model's mistake cannot reach a fab. Every stage has a deterministic check behind it, and the last one decides whether fab files exist. ## On the schematic | Check | What it catches | | - | - | | Pre-flight | Symbol and footprint names that do not exist. Unambiguous typos are corrected and listed; the rest are returned as findings. | | SKiDL compile | A script that does not build a netlist. The error goes back to the synthesizer with the code. | | ERC score | Unconnected pins, driver conflicts, missing power, single-pin nets. A ported electrical-rules check with a score. | | KiCad ERC | KiCad's own electrical-rules check on the written schematic. | | Floating subsystems | A cluster of parts with no path to the rest of the circuit. | | Footprints | A part with no footprint, or a custom IC without a real package. | | Sourcing | A part with no distributor listing in stock. Reported, with candidates. | A design review reads the passing circuit and can send it back with blocking findings. ## On the board | Check | What it catches | | - | - | | KiCad DRC | Clearance, track width, annular ring, hole-to-hole, copper-to-edge, courtyard overlaps, silkscreen on pads. Run by `kicad-cli pcb drc` with the project's rules after a zone refill. | | Fab minimums | The project carries the fab's floors: minimum track, minimum drill, copper-to-edge clearance. The JLCPCB preset adds the per-feature limits KiCad only has as custom rules, such as plated ring and hole-to-track spacing. | | Connectivity | KiCad's ratsnest. A stranded pad or a severed pour counts, even when the router reported the net as done. | | Parity | The board has exactly the footprints the netlist has. Mounting holes and fiducials the engine adds are marked board-only. | | Plane integrity | Islands, slivers and stranded pads on poured nets. | | Physics | Rail width against current, pair coupling and skew, impedance from the stackup. | ## The release gate Fab files are built only when both of these hold: 1. **Zero DRC errors** from KiCad, with the fab's rules. 2. **Nothing unconnected** in KiCad's ratsnest. A board that fails the gate is still yours. The KiCad project, the board and the DRC report are downloadable, the report names every open net and every violation, and the chat agent can diagnose it and run again. What you do not get is a `gerbers.zip` for a board that would come back wrong. "Mostly routed" is the most expensive kind of board, because the error surfaces after the fab order. Koppar reports it as a failed board, not as a result. ## The same checks for agents An agent driving Koppar over MCP, the CLI or REST gets the same gates. `submit_circuit` runs the schematic checks and returns blocking findings. `get_fab_status` says whether the board has earned its fab files and, if not, why. This documentation is built and hosted on [Mintlify](https://mintlify.com), a developer documentation platform.