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Before placement, one planning call turns the circuit into a board plan. Some of it is decided from the circuit. Some of it is read from what you said.

What you can state

Facts stated in the prompt are carried as stated facts, not as suggestions. They are never overridden by the planner. Everything else, say it and the planner takes it as intent: which connector sits on which edge, which parts group together, which sit near which, what stays off the board.

What the planner decides

  • Outline. Derived from the parts and the stated size.
  • Layers. 2 by default. 4 when the circuit needs it, or when a 2-layer board cannot close.
  • Net classes. Every net is a plain signal track unless a class says otherwise. Classes come from the circuit, from what you state, or from the net name.
  • Edge parts, groups, keepouts. Connectors on edges, decoupling by its IC, antennas kept clear of copper.

Net classes

Widths are a target and connectivity is the contract: where the geometry will not take the class width, the net is routed narrower rather than left open, and the width applied is reported. The classes are written into the KiCad project, so KiCad’s DRC checks the same rules Koppar did.

Fab presets

The project file carries the floors the copper is legal at: the router’s minimum track width, the minimum drill, and a 0.3 mm copper-to-edge clearance. The JLCPCB preset applies that fab’s published minimums as custom DRC rules, including the per-feature limits for plated rings and hole-to-track spacing that KiCad’s standard DRC does not cover. The preset note states that 0.15 mm drills and tracks under 0.127 mm cost extra at that fab.

Your own plan

Over MCP, the CLI or REST, the plan is yours. get_board_context returns the parts, their sizes, the stated facts and the plan schema; start_board takes a JSON object with board, stated, edge, chain, groups, near, side, fixed, keepouts and netClasses. The plan is clamped to what the board can take and returned as applied.